Field of the Invention
This invention relates generally to integrated circuits used as FET gate drive circuits, and more particularly to a voltage clamp circuit used to prevent the over-stress of the gate of a MOSFET power transistor.
2. Description of the Relevant Art
The problem addressed by this invention is encountered in circuits which drive the gate of an N-channel power MOSFET transistor which commonly requires a gate voltage greater than a Vcc voltage. FIG. 1, shows a typical prior art circuit for driving a load with a power transistor. In this circuit, the power transistor is an N-channel MOSFET transistor 10. The power transistor is off when the control signal is low since the output of inverter 2 will be high =which consequently turns P-channel transistor 6 off and N-channel transistor 8 on. Thus, the gate of power transistor 10 is pulled to ground through transistor 8 which effectively holds power transistor 10 off. Conversely, the power transistor 10 is turned on when the control signal goes from low to high since the output of inverter 2 is goes from a high to a low which turns transistor 6 on and transistor 8 off. Thus, the gate of power transistor 10 is pulled to a voltage B+ which turns power transistor 10 on. The turn-on time can be described as:
t=c*v/i where PA1 t=turn-on time PA1 c=the capacitance of the gate PA1 v=the gate turn-on voltage, and PA1 i=the current flow into the gate.
It has been observed in a typical switching mode power supply application operating at 100 kHz that the t should be less than 20 nanoseconds, the v is on the order of 10 volts, the c is on the order of 1,000 picofarads, and the i is on the order of 500 milliamps. In FIG. 1 as well as generally, the B+ voltage is higher and less regulated than the Vcc voltage. It is common for the B+ voltage to be generated from a battery and its associated charging circuit, from a charge pump circuit, or from other poorly regulated sources. Additionally, it is known in the industry that excessive gate voltage can cause punch through damage to the gate. The maximum safe gate voltage is process dependant and can typically range from 12 to 18 volts for typical BCD process technologies. Therefore, it is desirable to protect the gate of the power transistor from excessive B+ voltages to avoid electrical overstress since the B+ voltage is generally poorly regulated.
FIG. 2 illustrates a gate drive circuit which is the same as the gate drive circuit in FIG. 1, but has an additional zener diode 12 to protect the gate of the power transistor 10 from an excessive B+ voltage. In operations, the power transistor is turned on when the control signal is high and the output of the inverter 2 is low, as described in above. In this state, the gate of transistor 10 is driven to the B+ voltage (minus the Vds voltage drop of transistor 6) which charges the gate and turns the transistor on. Once the transistor is on, the circuit draws a very low current since, after the gate of transistor 10 is charged, transistor 6 only conducts enough current to maintain the charge, which is minimal.
If the voltage on the gate of power transistor 10 exceeds the threshold voltage of the zener diode 12, then zener diode 12 clamps the gate voltage to the threshold voltage. Thus, the gate voltage is limited to the threshold voltage and is protected against any higher voltages by the voltage clamp created by zener diode 12. However, the diode 12 is conducting as much current as is available to Charge the gate of the power transistor, which in the example above was on the order of 500 milliamps. Consequently, the circuit continues to draw a large current on the order of 500 milliamps even after the gate of transistor 10 has been charged.